For applications in the higher power range and in the higher current range, discrete circuit components, in particular semiconductor components, often are still much more economical than solutions with full monolithic integration. A switch system frequently comprises an integrated driver circuit and a suitable external device, for example in a form of a power transistor, thyristor or relay. For obtaining a high system reliability, the driver circuit must be able to detect overload conditions and switch off the switch system if required. For being adaptable to changing applications, the driver circuit must have a programmable response delay.
With known circuits, two solutions are common: current monitoring using a sensor resistor or overload detection by monitoring a voltage drop across the switch system, with the following explanations being based for example on a power transistor as switch system.
The solution using current monitoring involves a resistor connected in series with the power transistor for monitoring a load current thereof The voltage drop across this resistor is the criterion for turning off the power transistor. When the voltage drop exceeds a certain value, the power transistor will be turned off.
Most loads include a capacitive component. Turning on the power transistor abruptly thus will cause a large current spike even if the system is in a proper operation mode. To prevent erroneous turning off of the power transistor, this current spike must be masked. Masking of the current spike can be reached by inhibiting the protection circuit by means of a timer for a certain period of time. This period is dependent on the specific application and must therefore be programmable to meet multiple applications with one integrated circuit.
An example of such a known protection circuit with current monitoring is shown in FIG. 2. An integrated driver and overload protection circuit comprises three AND gates AND1, AND2 and AND3 as well as a timer, a comparator comp, an RS flipflop RSFF and a driver transistor M1 in the circuit arrangement shown in FIG. 2. This integrated circuit comprises external components in the form of an external power transistor Q1, an external senior resistor Rsense and an external RC circuit having a resistor Rt and a capacitor Ct. For connection to these external components, the integrated circuit requires six terminal pins, namely:
EN input terminal pin for the protection circuit logic PA1 Drive terminal pin for driving the power transistor PA1 Sense1 and Sense2: terminal pins for current monitoring PA1 TIME: terminal for timer programming PA1 GND: ground terminal pin
A timer adjustment is made for the specific application by means of the RC circuit Rt, Ct.
For turning on the external power transistor Q1, terminal pin EN has to assume a high potential. High potential at EN starts the timer and sets RS flipflop RSFF via AND2. As long as an input signal at EN remains on high potential, AND3 allows passage of an output signal of RSFF to the driver transistor M1. The timer inhibits the AND gate AND1 for a specific period of time that is adjustable by means of the external components Ct and Rt, whereby an overload signal delivered by the comparator is suppressed so as to prevent turning off due to capacitive loads. After this period of time, the timer releases AND1 again so that an overload protection signal delivered from an output of comparator comp can reach a resetting input R of RSFF. Resetting of RSFF effected thereby results in inhibiting of AND3, so that the high potential present at EN can no longer reach the gate of M1 via AND3. This leads to blocking of driver transistor M1 and consequently to turning off of power transistor Q1. For avoiding signal conflicts at the inputs of RSFF, AND2 prevents setting of RSFF again after the timer has released the overload protection function.
A circuit arrangement with monitoring of the voltage drop across a power transistor to be protected is depicted in FIG. 3. The integrated circuit part identically corresponds to the integrated circuit part of the circuit arrangement shown in FIG. 2. FIG. 3 differs from FIG. 2 in so far as there is no sensor resistor provided and an inverting input of comparator comp serving as overload detector is connected to a collector terminal of power transistor Q1.
Just as in FIG. 2, the integrated circuit part of FIG. 3 needs six terminal pins, with the sole difference that the terminal pin associated with the inverting input of comp has a different function.
Circuits with current monitoring usually require a voltage drop across a sensor resistor in the range of some hundred mV. A product of this voltage drop and a current flowing through the sensor resistor contributes to an overall power dissipation of the system. When monitoring the voltage drop across the power transistor, the overall power dissipation of the system can be reduced by omission of the sensor resistor.
During a turn on edge of power transistor Q1, which is dependent upon a capacitive part of the load, the voltage drop across power transistor Q1 is higher than a value at which the protection circuit would force deactivation of the power transistor. This is why in this case, too, the overload detection must be suppressed for a certain period of time. This period, which is dependent both on the load and on the power transistor, must be programmable to render possible matching to different embodiments and applications.
In case of the circuit shown in FIG. 3, involving monitoring of the voltage drop across power transistor Q1, it is indeed sufficient to have three external circuit components, namely Q1, Ct and Rt, but just as in case of FIG. 2 there are six terminal pins required for the integrated circuit.
A mode of operation of the integrated circuit part in FIG. 3 is identical with a mode of operation of the integrated circuit part in FIG. 2.